This application is based upon the prior Japanese Patent Applications No. 11-062269, filed Mar. 9, 1999; and No. 11-369758, filed Dec. 27, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a technique of controlling the threshold voltage of a nonvolatile semiconductor memory and, more particularly, to a technique of shifting the threshold voltage of an overerased cell to an appropriate threshold voltage range.
A nonvolatile semiconductor memory conventionally uses a scheme of injecting hot electrons from the drain side to the floating gate to write data in a selected memory cell (to be simply referred to as a cell hereinafter) and removing electrons from the floating gate to the source diffusion layer or to the substrate through the entire channel surface on the basis of the mechanism of a Fowler-Nordheim tunnel current to erase data. Cells constitute one block in units of, e.g., 64 kbytes (512 kbits). In the erase, data are flash-erased at once in units of blocks. The distribution of the threshold voltage of the cell in the flash erase will be described with reference to FIG. 1.
As shown in FIG. 1, erase operation is repeatedly performed until the latest erased bit obtains a desired threshold voltage VTH. This voltage is called an erase verify voltage VEV. The value of the erase verify voltage VEV is preferably set as small as possible to increase a difference xcex94V between the voltage applied to a selected word line and the value of the erase verify voltage VEV in the data read. The larger the voltage difference xcex94V becomes, the larger the ON current flowed by the cell becomes. Hence, the data can be read out at a higher speed, and the performance of the nonvolatile semiconductor memory improves.
In flash erase in units of blocks, since the erase speed varies between the cells, the threshold voltage VTH after the flash erase varies with a certain distribution width D, as shown in FIG. 1. The threshold voltage VTH varies due to various reasons, and generation or disappearance of a trap in the gate oxide film is also related. For this reason, when the rewrite is repeated, the erase speed of a cell suddenly increases or returns to the previous speed again.
When a cell (to be referred to as an overerased cell hereinafter) whose threshold voltage VTH becomes too low because of a high erase speed, e.g., a cell whose threshold voltage VTH is equal to or lower than the voltage applied to unselected word lines in the data read is generated, several problems occur in the subsequent write operation or read operation.
FIG. 2 is a circuit diagram showing the cell array of a nonvolatile semiconductor memory (flash memory).
As shown in FIG. 2, cells MC are arranged as a matrix in the cell array. A drain terminal D of each cell is connected to a bit line BL (BL1, BL2, BL3, BL4, . . . ) running in the horizontal direction in FIG. 2, and a control gate CG is connected to a word line WL (WL1, WL2, WL3, WL4, . . . ) running in the vertical direction in FIG. 2. The source terminal of each cell is connected to a source line SL running in the vertical direction in FIG. 2.
Problems which occur when an overerased cell is generated in the cell array will be described with reference to FIG. 3. FIG. 3 shows the biased state of the cell array in the write operation.
As shown in FIG. 3, assume that an overerased cell (e.g., a cell MC32 in FIG. 3) is generated in the cell array. The overerased cell MC32 flows an excess leakage current ILEAK from its drain terminal D to source terminal S. For this reason, in the subsequent operation, the excess leakage current ILEAK will flow to the bit line BL2 to which the overerased cell MC32 is connected. For example, in the write operation generally performed next to the erase operation, the excess leakage current ILEAK reduces the voltage of the bit line BL2. For this reason, when data is to be written in a cell (e.g., a cell MC12 in FIG. 3) connected to the bit line BL2, the write time increases, or in some cases, the write is disabled.
In a recent nonvolatile semiconductor memory, the bias voltage to be applied to the bit line BL in the write operation is boosted from a low power supply voltage using a charge pump circuit. In such a nonvolatile semiconductor memory, drop of the voltage on the bit line BL particularly tends to occur due to the leakage current ILEAK.
Even when the write is possible, if the leakage current ILEAK flows to the bit line BL in the read operation, data of all cells with drain terminals connected to the bit line BL may be erroneously detected as data xe2x80x9c1xe2x80x9d. Even when the detection error for data xe2x80x9c1xe2x80x9d is avoided, the read speed from the cell with data xe2x80x9c0xe2x80x9d may be reduced by the leakage current ILEAK.
The generation frequency of such an overerased cell increases as the erase verify voltage VEV becomes low.
On the other hand, however, since the performance of the nonvolatile semiconductor memory can improve as the erase verify voltage VEV is lowered, as described above, the erase verify voltage VEV is required to be as low as possible.
To meet this requirement, it has been proposed to employ a function of restoring the excessively low threshold voltage VTH to a desired value after the flash erase.
As one method for this, the bit line BL connected to the cell whose threshold voltage VTH is too low is detected, and a high voltage is applied to the bit line BL while fixing the voltage of the word line WL to a potential of, e.g., almost 0 V. With this operation, the excessively low threshold voltage VTH is raised to a desired value. This method is disclosed in S. Yamada, IEDM Tech. Dig, pp. 307-310 (1991) and currently called a self-convergence method. FIG. 4 shows the biased state of a cell in the self-convergence operation.
With the self-convergence method, however, when the desired threshold voltage is relatively high, a very long time is required to raise the threshold voltage VTH to the desired value, unlike, e.g., the normal write operation. As is apparent from data disclosed in the above reference, a time of several ms or less suffices to raise the threshold voltage VTH to 0 V or more, though a time of several ten ms is required to raise the threshold voltage to 1 V or more. For a recent memory cell having a short channel length, the threshold voltage rises to about xe2x88x921 to 0 V in a shorter time: for example, the threshold voltage rises to about 0 V in, e.g., about 1 ms. The threshold voltage rises to xe2x88x921 V in a much shorter time. However, to increase the threshold voltage to a higher level, a long time is often necessary because the speed of rise is saturated even in a microfabricated device. For this reason, when the number of cells whose threshold voltages VTH must be raised is large, an impractical time is required for the entire chip to increase the threshold voltages VTH of all the cells to a desired value of, e.g., 1 V or more using only this method.
In addition, when a plurality of overerased cells are connected to one bit line BL, a leakage current flows through the plurality of overerased cells. Hence, in the self-convergence operation, the voltage of the bit line BL drops, and only this may make the time required to boost the threshold voltage VTH to a desired value very long.
As another method, an overerased cell is detected by scanning the voltage of the word line WL at a predetermined voltage, the detected overerased cell is selected, and desired voltages are applied to the word line WL and bit line BL connected to the selected overerased cell to write data until the threshold voltage VTH rises to a desired value. This method is disclosed in U.S. Pat. No. 5,568,419 and generally called a weak-program method. FIG. 5A shows the biased state of a selected cell in the weak-program operation.
In this weak-program method, electrons are injected from the drain to the floating gate by positively applying desired voltages to the word line WL and bit line BL connected to the overerased cell. For this reason, as in the normal write operation, the threshold voltage VTH can be boosted to a desired value by supplying a write pulse in units of xcexcs to the selected word line and bit line.
In the weak-program method, an overerased cell is selected, and a weak write is executed, unlike the self-convergence method. For this reason, as shown in FIG. 5B, in an unselected cell, the voltage of the word line WL (unselected word line) can be set to, e.g., xe2x88x921 V, thereby minimizing the current flowed by another overerased cell present on the same bit line BL.
In the weak-program method, however, when the threshold voltage VTH of a cell lowers to a very small value, the overerased cell may not be accurately detected to cause an operation error. This will be described with reference to FIG. 6.
As shown in FIG. 6, unselected word lines (WL2, WL3, WL4, . . . in FIG. 6) are set to a voltage of, e.g., xe2x88x921 V. Each of the cells connected to the unselected word lines is cut off if its threshold voltage VTH exceeds xe2x88x921 V.
On the other hand, the selected word line (WL1 in FIG. 6) is set to a voltage higher than the threshold voltage VTH to be detected by a predetermined value, and a read bias voltage of, e.g., 0.5 V is applied to the selected bit line (BL2 in FIG. 6) to make it perform the read operation. For example, to detect a cell whose threshold voltage VTH is equal to or lower than 1 V, a voltage of, e.g., 2 V is applied to the selected word line WL1. In addition, a voltage of 0.5 V is applied to the selected bit line. The unselected bit lines (BL1, BL3, BL4, . . . in FIG. 6) are, e.g., OPEN.
With this biased state, the cell (cell MC12 in FIG. 6) to be detected is selected, and it is detected whether an ON current ION equal to or larger than a predetermined value flows to the bit line BL2. If not, it is determined that the threshold voltage VTH is xe2x80x9chigher than 1 Vxe2x80x9d, and xe2x80x9cthe weak-program operation is unnecessaryxe2x80x9d.
If the ON current ION equal to or larger than the predetermined value flows, it is determined that the threshold voltage VTH is xe2x80x9cequal to or lower than 1 Vxe2x80x9d, and xe2x80x9cthe weak-program operation is necessaryxe2x80x9d.
In this way, it is detected whether the selected cell MC12 is an overerased cell. If so, the weak-program operation is executed for the selected cell MC12.
Assume that a cell whose threshold voltage VTH is lower than xe2x88x922 V is connected to the same bit line BL2 (for example, a cell MC42 in FIG. 6). In this case, since the voltage of the unselected word line WL4 is xe2x88x921 V, the unselected cell MC42 flows the ON current ION equal to or larger than the predetermined value. As a consequence, the threshold voltage VTH of the cell MC12 to be detected is determined to be xe2x80x9cequal to or lower than 1 Vxe2x80x9d regardless of the state of the threshold voltage VTH.
If the threshold voltage VTH of the selected cell MC12 is higher than 1 V, i.e., the threshold voltage has an appropriate value, the threshold voltage VTH of the selected cell MC12 is erroneously detected. For this reason, the weak-program operation is executed for the selected cell MC12 having the appropriate threshold voltage VTH.
The weak-program operation caused by the detection error is repeatedly performed while the unselected cell MC42 flows the ON current ION equal to or larger than the predetermined value. As a result, the threshold voltage VTH of the selected cell MC12 may continuously increase, exceed the erase verify voltage VEV, and then exceed a value for the xe2x80x9c1xe2x80x9d read in the data read.
When the threshold voltage VTH exceeds the value for the xe2x80x9c1xe2x80x9d read, it means that the data is not erased (xe2x80x9c0xe2x80x9d is read in the data read) although the data is erased (xe2x80x9c1xe2x80x9d is read in the data read). The chip with this phenomenon is xe2x80x9cdefectivexe2x80x9d.
Assume that a cell (e.g., the cell MC32 in FIG. 7) whose threshold voltage VTH is between xe2x88x922 V (inclusive) and xe2x88x921 V (exclusive) is connected to the same bit line BL2, as shown in FIG. 7. In this case, the detection error described with reference to FIG. 6 does not occur, though the unselected cell MC32 flows the leakage current ILEAK. This leakage current ILEAK is added to the current flowed by the selected cell MC12 to be detected. This also causes the overwrite in the selected cell MC12.
Assume a design in which the voltage of the selected word line WL1 is set to 2 V, and when the ON current ION flowing to the selected bit line BL2 is, e.g., 10 xcexcA or less, it is determined that the threshold voltage VTH of the selected cell MC12 exceeds 1 V, and the weak-program operation is ended.
However, if the unselected cell MC32 is flowing the leakage current ILEAK of 5 xcexcA, the weak-program operation is not ended unless the ON current ION of the selected cell MC12 is 5 xcexcA or less. This means that although the threshold voltage VTH of the selected cell MC12 already exceeds 1 V and has an appropriate value, the weak-program operation is not ended. This may cause the overwrite in the selected cell MC12.
If the overwrite occurs, the above phenomenon that the data is not erased although it is erased occurs.
In addition, when the threshold voltage VTH is still lower than the voltage for the xe2x80x9c1xe2x80x9d read but is equal to or higher than the erase verify voltage VEV, this causes a shortage in the voltage difference xcex94V, i.e., a shortage in read current margin. The shortage in margin current delays the read operation.
Furthermore, when the unselected cell MC32 flows the leakage current ILEAK, the voltage of the bit line BL2 becomes lower than the original set value due to the leakage current ILEAK.
In the weak-program operation, unselected word lines are fixed to xe2x88x921 V, and a voltage is applied to the drains of the unselected cells MC22, MC32, MC42, which share the bit line BL2 with the selected cell MC12. For this reason, in these unselected cells, the threshold voltages VTH are increased by the same mechanism as that of, e.g., self-convergence. When the threshold voltage VTH of the unselected cell MC32 increases and exceeds xe2x88x921 V, the unselected cell MC32 is set in the xe2x80x9ccutoff statexe2x80x9d, and the leakage current ILEAK suddenly decreases. As a consequence, the voltage of the bit line BL2, which is lower than the original set value, is suddenly restored to the original set value (suddenly rises).
As described above, the voltage of the bit line BL2 connected to the unselected cell MC32 whose threshold voltage VTH is lower than xe2x88x921 v sometimes suddenly increases, so the write speed or write amount of the weak-program operation cannot be controlled as designed. When the voltage of the bit line BL2 suddenly rises, data beyond the desired threshold voltage VTH may be written in the selected cell MC12.
This phenomenon especially conspicuously occurs when the step-up method is used together in the weak-program operation. In the step-up method, every time the weak-program operation is repeated for the selected cell MC12, the voltage of the word line WL1 is stepped up. The step-up method is disclosed in, e.g., H. Shiga, Symposium of VLSI Circuit Technical Digest, pp. 33-36 (1999).
The step-up method can increase the threshold voltage VTH to a desired value at a much higher speed as compared to the method of repeating the weak-program operation while keeping the voltage of the selected word line WL1 constant.
However, since the leakage current ILEAK flows to the bit line BL2 connected to the cell MC32 whose threshold voltage VTH is lower than xe2x88x921 V, the voltage value of the bit line BL2 becomes smaller than the original set value, and the weak-program speed lowers. For this reason, the number of times of repetition of weak-program operation increases, and the number of step-up operation of the selected word line WL1 increases. Consequently, the voltage of the selected word line WL1 increases to a very large value.
In use of such a step-up method, when the voltage of the bit line BL2 is suddenly increased by the above mechanism, a write with a very large value is performed. Hence, the phenomenon that data is written beyond the desired threshold voltage VTH especially conspicuously occurs.
The same phenomenon as described above particularly readily occurs in a nonvolatile semiconductor memory that simultaneously reads/writes data. FIG. 8 is a block diagram of such a nonvolatile semiconductor memory.
As shown in FIG. 8, a nonvolatile semiconductor memory which simultaneously executes the data read and write for a plurality of bit lines has a plurality of I/O circuits 109 in one block. Each of the I/O circuits 109 is connected several bit lines, e.g., 16 bits lines BL1 to BL16, BL17 to BL32, . . . through a column selector 107. A column decoder 108 supplies column selection signals corresponding to a column address to the plurality of column selectors 107 through column selection lines (CSL1 to CSL16). Each of the plurality of column selectors 107 selects one of the 16 bit lines in accordance with the column selection signal and connects the selected bit line to the I/O circuit 109. The output of a charge pump circuit 104 is connected to the connection paths for connecting the I/O circuits 109 and column selectors 107. In the weak-program operation, a write bit line bias voltage is simultaneously supplied from one charge pump circuit 104 to the plurality of bit lines.
In this nonvolatile semiconductor memory, when even one of the plurality of selected bit lines has an excess leakage path, the voltage output from the charge pump circuit 104 lowers. As a result, the voltage values of all of the plurality of selected bit lines become smaller than the original set value.
In the nonvolatile semiconductor memory shown in FIG. 8, even when the self-convergence method is used, the time required for self-convergence increases. This is because when even one of the plurality of selected bit lines has an excess leakage path, the voltage values of all of the plurality of selected bit lines become smaller than the original set value, as described above.
A case wherein a cell having a very low threshold voltage is present on the same bit line has been described above for the descriptive convenience.
Actually, however, even when a number of cells having relatively low threshold voltages are present, the same problem of operation error is posed when the sum of leakage currents is large.
A measure against an operation error in the weak-program operation has disclosed in Jpn. Pat. Appln, KOKAI Publication No. 8-106793 filed by Takahashi et al., in which after a bit line with a leakage is detected, the weak-program operation is executed for all cells on the bit line, and after the leakage is eliminated, a cell having a threshold voltage lower than a desired threshold voltage is detected, and the weak-program operation is executed under the same bias conditions as those for the first weak-program operation. However, this method also has two serious problems. As one problem, when the write is performed in all cells under the same bias conditions as those for the weak-program operation, the write operation is performed even for a cell whose threshold voltage is high and close to the erase verify voltage. Hence, data is further written in that cell, soothe voltage exceeds the erase verify level. FIG. 17 of Jpn. Pat. Appln, KOKAI Publication No. 8-106793 shows a state wherein the threshold voltage of a cell having a high threshold voltage is reduced by the weak-program operation. However, the threshold voltage normally often increases in an actual device in which the erase verify voltage is set to, e.g., 2.5 V or less, and the word line voltage in the weak-program operation is set to 4 V. The actual characteristic is also shown in H. Shiga et al., Symposium of VLSI circuit Technical Digest, pp. 33-36 (1999). As the other problem, a long time is required when the weak-program operation is sequentially executed for all cells. The reason for this is as follows. Since the number of cells connected to a single bit line is 1K to 2K, and it cannot be determined which cell needs the write, the write must be performed while sequentially increasing the voltages of word lines of all cells on that bit line, though the write time for each cell can be shortened. In addition to the actual application time for a memory cell, a time is also required to increasing/decreasing the voltage while switching the word lines. Hence, even when the threshold voltage is to be adjusted to a predetermined range in two steps, for example, the first step for all cells,on a single bit line, and the second step for necessary cells, it is not preferable to execute the two steps disclosed in the prior art using the same potential from the viewpoint of the risk of operation error generation and the operation speed.
The present invention has been made in consideration of the above situation, and has as its main object to provide a nonvolatile semiconductor memory which can restore the threshold voltage of a memory cell, which falls outside a desired range, to the desired range while suppressing any operation error and detection error without reducing the operation speed, and a threshold voltage control method for the memory.
In order to achieve the above object, according to the present invention, the threshold voltages of a plurality of memory cells are shifted at once to a range for which one of the upper and lower levels is set to a first level, and then, for the plurality of memory cells including a memory cell deviating from the second level close to the first level, the other of the upper and lower limits of the shifted threshold voltages is shifted at once to the second level under a first bias condition. As the bias condition at this time, an appropriate bias voltage is applied so that no problem is posed even when the voltage is applied to a cell which does not actually deviate from the second level, and a cell that deviates from the second level reaches the second level at a high speed. More specifically, a so-called self-convergence method of setting the word lines to a low voltage of 0 to xe2x88x921 V and applying a voltage of 4 to 5 V to a bit line which is detected as a bit line including a cell deviating from the second range is used.
Note that in this operation, a bias may be applied to even a bit line including no memory cell deviating from the second level to simplify the circuit operation.
After this, the other of the upper and lower limits of the threshold voltages shifted to the second level is shifted to the third level closer to the first level than the second level under the second bias condition different from the first bias condition. For example, only a cell deviating from the second level is selected, a voltage of 2 V is applied to the word line of the cell, and a voltage of 4 to 5 V is applied to the drain of the cell. As described above, under the second bias condition, when the same charge injection mechanism is used for the first and second bias conditions, the word line voltage is set to be higher than that under the first bias condition. The word line voltage can be increased to the desired third level in a shorter time by using a step-up method of sequentially boosting the voltage while monitoring the write speed of cells. An unselected word line is fixed to a voltage which does not generate a leakage current that poses a problem for a memory cell at the second level. For example, the voltage is xe2x88x921 to 0 V.
In such a nonvolatile semiconductor memory, first, the other of the upper and lower limits of the threshold voltages of the plurality of memory cells is shifted at once to the second level in a short time. For this reason, in shifting the other of the upper and lower limits of the threshold voltage to the third level, the plurality of memory cells can. be reliably cut off by applying an appropriate bias to unselected word lines on the basis of the second level. Hence, in shifting the other of the upper and lower limits of the threshold voltage to the third level, even when the weak-program method is used, the threshold voltage can be shifted to a desired range while suppressing, e.g., an operation error and detection error.
Since the other of the upper and lower limits of the threshold voltage is shifted to the third level stepwise, and appropriate bias conditions are used for the respective shift steps, the shift amount per step can be small, as compared to a case wherein the threshold voltage is boosted to the third level at once. For this reason, in shifting the threshold voltage to the second level, for example, even when a self-convergence method of setting all word lines to 0 V or a potential close to 0 V and applying a voltage to the bit line of all cells on the same bit line at once is used, the speed of operation of shifting the threshold voltage is hardly reduced. In addition, after a cell deviating from the second level is made reliably detectable, a memory cell deviating from the third level is detected. For this memory cell, a bias condition different from that in shifting to the second level is set, and the threshold voltage is shifted to the desired value in a short time.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.